The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as about 0.18 microns, increased transistor and circuit speeds, high reliability and increased production throughput for economic competitiveness. The reduction of design features to 0.25 microns and under challenges the limitations of conventional methodology, particularly conventional photolithographic and polishing techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically appropriately doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer is deposited on the first dielectric layer. The metal layer is typically a composite comprising a first metal layer such as tungsten or titanium, a second intermediate primary metal layer such as aluminum or an aluminum alloy, and an upper anti-reflective coating which also serves as an etch stop layer such as titanium nitride. A photoresist mask is formed on the metal layer having a pattern defining a plurality of conductive features in accordance with design requirements. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin on glass (SOG) is then applied to the resulting conductive pattern to fill the gaps. Another dielectric layer is then deposited, such as silicon oxide derived from tetraethyl orthosilicate (TEOS) or silane by plasma enhanced chemical vapor deposition (PECVD). Planarization is then effected, as by etching or chemical mechanical polishing (CMP).
The conductive pattern typically comprises a plurality of metal features, some of which have different sizes. For example, a typical conductive pattern comprises a dense array of metal features, typically separated by gaps having a width of less than about 1 micron, e.g., about 0.375 microns for metal features of about 0.25 microns. A metal feature neighboring a leading or trailing metal feature of a dense array, however, may be considerably larger than the metal features of the dense array. For example, neighboring metal features may have an upper surface area greater than the upper surface area of a leading or trailing metal feature of a dense array such that, upon depositing a gap filling dielectric layer, a step is formed with increasing height between the relatively smaller leading or trailing metal feature and the relatively larger neighboring metal feature. Such steps can have a height in excess 3,000 .ANG. and may be as high as 1 micron or greater. It is extremely difficult to planarize an oxide layer deposited on such steps.
Moreover, as feature sizes shrink to 0.25 microns and under, planarization becomes even more critical in that irregular topography may exceed the depth of focus limitations of conventional photolithographic techniques. Accordingly, as design features shrink to 0.25 microns, it becomes increasing critical to minimize or reduce the formation of steps when gap filling patterned conductive layers.
There exists a need for semiconductor methodology for improved planarization of dielectric layers. There exists an even greater need for improved planarization of dielectric layers in manufacturing semiconductor devices having a feature size of about 0.25 microns or under.